Semiconductor devices or die are typically contained within a larger housing or "package" which provides mechanical support for the semiconductor die also protects it from physical damage. A typical semiconductor package includes an area sized to receive the semiconductor die, commonly referred to as a "window" and is provided with one or more (and typically tens or hundreds) of leads or circuit paths which allow the semiconductor die placed within the window of the package to be electrically connected to leads or terminals located on exterior portions of the package. The resulting semiconductor device assembly (i.e., the package and die) may then be mounted to a suitable printed circuit board (PCB) by any of a wide range of processes well known in the art.
Several different methods have been developed over the years to electrically connect the various input or output (I/O) terminals or "pads" on the semiconductor die to the corresponding leads provided on the package substrate. For example, one method, generically referred to as wire bonding, individually connects each of the I/O pads on the die with the various leads provided on the package with a very fine wire (e.g., wire having a diameter of about 18 microns or so). The wires are bonded or welded, one at a time, to the pads on the semiconductor die and on the package substrate using a special tool, such as a wedge or a capillary, and a combination of heat, pressure, and/or ultrasonic energy. These processes are generically referred to as thermocompression or thermosonic bonding.
Although the wire bonding process was originally done manually, with the operator's skill controlling every aspect of the bonding process, it has progressed rapidly to a fully automated process as the density of I/O connections has increased. In the automated wire bonding process, an automatic wire bonding machine senses the locations of the I/O pads on both the semiconductor die and the package substrate and then automatically connects the appropriate pads with the fine wire. Such automated wire bonding processes are well-developed and have kept pace with the ever increasing number of connections and shrinking bond pad sizes on the semiconductor die. For example, it is not uncommon to bond semiconductor die requiring 300 connections and having two rows of alternating perimeter bonding pads with pad sizes as small as 50.times.50 .mu.m (2.times.2 mils) with 100 .mu.m (4 mils) between on-row pad centers.
Other techniques that may be used to electrically connect the semiconductor die to the package substrate include, but are not limited to, tape automated bonding (TAB) processes and any of a variety of the newer so-called "flip chip" processes.
While the foregoing device architectures and methods for electrically connecting the semiconductor die to the various leads provided on the package substrate work well and are being used, continuing developments in integrated circuit technology are resulting in semiconductor die having an ever increasing number of I/O pads as well ever increasing and substantial current requirements. For example, a 40 watt device operating at 5 volts requires 8 amperes of supply current, whereas the same device operating at 2 volts requires 20 amperes of supply current. Since most die architectures require that such power be provided to the die at locations near the center of the chip, and not at the periphery, where the I/O bond pads are typically located, it has proven difficult to provide the required high current supply paths. That is, since the wires used in the wire bonding process are extremely fine (typically about 18 microns in diameter), a single wire cannot be used to carry the high currents required by some of the newer, higher powered semiconductor die.
One method that has been used in the past to overcome the limited current carrying ability of the bond wires is to utilize a plurality of wires arranged in parallel to provide redundant supply current and ground paths for the semiconductor die. While such parallel redundant wiring techniques are effective from a functional standpoint, they require many redundant bond pad sites, which reduces by a like amount the number of bond pad sites available for device I/O. Other problems relating to the use of multiple redundant bond wires to supply the operating current to the die include, but are not limited to, problems relating to resistive power losses in the wires, high inductance, signal cross-talk, and capacitance effects.
While the newly developed "flip chip" processes ameliorate some of the foregoing problems by providing shorter die-to-package connections, some of the gains are offset by the consequent difficulties the flip chip architecture imposes on the wiring contained in the package substrate. That is, it is still necessary to provide a relatively large circuit path through the highly nested wiring contained on the package substrate in order to provide the required power and ground connections to the face of the semiconductor die. Another problem is that flip chip processes typically require specially designed fabrication devices and jigs which are not currently widely used.
Consequently, a need remains for semiconductor package assembly capable of providing the relatively the high currents required by some of the newer, higher powered semiconductor devices while at the same time minimizing resistive power losses, as well as problems resulting from high inductance, signal cross-talk, and capacitance effects that are typically associated with currently available parallel bond wire architectures. Additional advantages could be achieved if such an improved package assembly could be fabricated with currently available semiconductor package fabrication devices and jigs.